While a scalar processor is a processor whose instructions operate on a single data, a vector processor refers to a processor that implements instructions operating on an array of data. In summary, a 1-bit branch predictor mispredicts the first and last branches of a loop. Therefore, it incorrectly predicts that the branch should be taken when the loop is first run again. Unfortunately, if the loop is run again, the branch predictor remembers that the last branch was taken. This is a correct prediction until the last branch of the loop, when the branch does get taken. While the loop is repeating, it remembers that the beq was not taken last time and predicts that it should not be taken next time. The loop repeats 10 times, and the beq out of the loop is taken only on the last time.īeq $s0, $t0, done # if i = = 10, branch to doneĪ one-bit dynamic branch predictor remembers whether the branch was taken the last time and predicts that it will do the same thing the next time. To see the operation of dynamic branch predictors, consider the following loop code from Code Example 6.20. The table, sometimes called a branch target buffer, includes the destination of the branch and a history of whether the branch was taken. Dynamic branch predictors maintain a table of the last several hundred (or thousand) branch instructions that the processor has executed. Therefore, most processors use dynamic branch predictors, which use the history of program execution to guess whether a branch should be taken. This is called static branch prediction, because it does not depend on the history of the program.įorward branches are difficult to predict without knowing more about the specific program. The simplest form of branch prediction checks the direction of the branch and predicts that backward branches should be taken. Loops tend to be executed many times, so these backward branches are usually taken. Some branches occur when a program reaches the end of a loop (e.g., a for or while statement) and branches back to repeat the loop. Recall that our pipeline from Section 7.5.3 simply predicted that branches are never taken. To address this problem, most pipelined processors use a branch predictor to guess whether the branch should be taken. Thus, the branch misprediction penalty gets larger, because all the instructions issued after the mispredicted branch must be flushed. As pipelines get deeper, branches are resolved later in the pipeline. The branch misprediction penalty is a major reason for increased CPI. Harris, in Digital Design and Computer Architecture (Second Edition), 2013 7.8.2 Branch PredictionĪn ideal pipelined processor would have a CPI of 1. Patt, "A Comprehensive Instruction Fetch Mechanism for a Processor Supporting Speculative Execution", Proceedings of the 25th Annual Symposium on Microarchitecture, Portland, Oregon, December 1992.David Money Harris, Sarah L. Tomasulo, "An efficient Algorithm for Exploiting Multiple Arithmetic Units", IBM Journal, vol. Sun95.SUN, "UltraSparc: Next Generation Superscalar 64- Bit Sparc", CompGoogle Scholar.SPEC92.SPEC 92 - Technical Manual - Rev.Weiss, "Power and PowerPC, Principles, Architecture, Implementation", Morgan Kaufmann Publishers, Inc., 1994 Google Scholar Digital Library Pleszkun, "Implementation of Precise Interrupts in Pipelined Processors", Proceedings of the 12th Annual International Symposium on Computer Architecture, June 1985 Google Scholar Digital Library Smith, "Tracing with Pixie", Stanford University, April 1991 Google Scholar Moto91.Motorola, "MC88110: Second Generation RISC Microprocessor User's Manual", 1991.Mips94.bliPS, "R10000 Microprocessor Product Overview", October, 1994 Google Scholar.Johnson, "Superscalar Microprocessor Design, Prentice-Hall, 1991 Google Scholar Inte93.Intel, "Pentium Processor User's Manual", 1993 Google Scholar.IbMo94.IBM, "PowerPC 604 RISC Microprocessor Technical Summary", IBM Advance Information, MPR604TSU-1, 1994 Google Scholar.Yan-Tek Hsu, "Designing the TFP Microprocessor", IEEE Micro, April 1994 Google Scholar Digital Library Dec95.DEC, "Scheduling and Issuing Rules for the Alpha 21164", Product Documentation, November 1994 Google Scholar.Patt, "An Investigation of the Performance of Various Dynamic Scheduling techniques", Proceedings of the 25th Annual International Symposium on Microarchitecture, Decem-ber 1992 Google Scholar Digital Library
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